As ESD protection, snapback-based solutions need to have a trigger voltage that is higher than the supply voltage of the chip they are protecting. However, in some applications, noise spikes and system level events are a common occurrence. If the difference between the chip's supply voltage and the snapback-based solution's trigger voltage is not high enough, these events can trigger the ESD protection. If the snapback voltage, and thus the holding voltage, is below the supply voltage, latch-up can occur.
Some of the current solutions include increasing the holding voltage such that certain elements are placed in series with the ESD protection. All current going the ESD protection must also run through these elements, which causes an extra voltage drop over them. This also means that to maintain the protection structure's holding current, a voltage is needed over these series elements. This effectively increases the holding voltage. A number of elements can be placed in series to the holding voltage above the supply voltage. The downside of this technique is that as you are dealing with relatively higher supply voltages and more series elements are needed. This means increased area consumption and increase in voltage does not always scale well with the number of devices for larger numbers (due to e.g. the parasitic SCR when using holding diodes). For high voltage technologies where snapback devices have very low holding voltages w.r.t. the supply voltage, this approach becomes very difficult. An example of this approach can be found in U.S. Pat. No. 6,768,616.
Another solution is to increase the trigger current via the feedback mechanism of the snapback device. This is hindered by adding low resistive leakage paths for the feedback current. For an SCR this is accomplished by connecting low value resistors to one or both gates. It is then more difficult for the feedback current to build up a voltage over the base-emitter junction of the bipolar transistor or transistors. This in turn results in lower additions to the feedback current. This technique can effectively prevent snapback devices from triggering in events where the current content is limited in some way (e.g. noise spikes). For events with a high current content however, the devices will trigger when the trigger voltage is reached, leading to snapback. Again, if the holding voltage of the device is lower than the supply voltage, this leads to latch-up. An example of this approach can be found in U.S. Pat. No. 6,803,633.
U.S. Pat. No. 6,281,527 and 6,147,369 disclose electrostatics discharge protection circuit with high trigger current. The disadvantage of these patents is that the trigger current is increased.
U.S. Pat. No. 5,493,133 is similar in structure as the U.S. Pat. Nos. 6,281,527 and 6,147,369 described above, and further includes another function by adding a second collector for conducting the reverse current though a PNP. Also, U.S. Pat. No. 5,493,133 fails to disclose any type of influence to trigger the SCR.
In U.S. Pat. No. 6,433,368, the ESD protection circuit includes an extra collector added in the Nwell; however, the disadvantage of this extra collector is that the SCR then no longer functions as a SCR. Also, a zener diode is placed in series with the cathode of the SCR, which lowers the failure current resulting in only the PNP conducting current. Also the P+ is connected direct to ground resulting in a higher trigger current.
In U.S. Pat. No. 6,570,226, in the ESD protection circuit the second collector of the PNP is connected to the second collector of the NPN. This way, the Nwell/P+ junction in series with an N+/Well junction will be the trigger of the SCR instead of the Nwell/PWell breakdown, resulting in lower trigger voltage. Since these seed collectors are not coupled to anode or cathode they will not serve to increase the holding voltage/current.
U.S. Pat. No. 7,123,054 also uses a second NPN in the ESD protection circuit, but it is separate bipolar transistor, thus falls to operate as an SCR. Further disadvantage is that trigger current is also increased.
U.S. Pat. No. 6,720,624 adds a P+ emitter to the drain of the ESD device resulting in both usage of larger area and increase in trigger current.
In U.S. Patent Publication No. 2004/0100745, the parasitic resistance of the SCR in the ESD circuit is also shunted to ground (P+ in substrate). Further, by placing the P+ over the Nwell, the spacing between anode cathode becomes larger due uncertainly about the exact location of the Nwell.
“Dynamic Holding Voltage SCR (DHVSCR) Device for ESD Protection with high latch-up Immunity”, Zi-Pin Chen et. al. also discloses a resistor to be a MOS transistor placed in the LAC (between anode and cathode) similar to the technique described in U.S. Pat. No. 6,803,633 which leads to latch up.
Thus, there is a need in the art to provide a protection technique for ESD protection that overcomes the disadvantages of the above discussed prior art where an increase in trigger voltage/holding is required during normal operation and thus a better latch-up immunity.